1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having memory cells on multiple layers.
2. Description of the Related Art
Requirements for high-density memories have accompanied advances in the development of semiconductor fabrication techniques. Various methods have been proposed to satisfy such requirements, including, for example, a memory device having a three-dimensional array structure (hereinafter, referred to as “3D memory device”). Examples of 3D memory devices are described in U.S. Pat. No. 5,835,396, entitled “Three-Dimensional Read-Only Memory,” U.S. Pat. No. 6,034,882, entitled “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication,” and U.S. Pat. No. 7,002,825, entitled “Word Line Arrangement Having Segmented Word Lines,” the contents of which are hereby incorporated by reference.
A 3D memory device includes memory cell arrays that are respectively formed on multiple semiconductor material layers. The semiconductor material layers may include a well-known silicon semiconductor substrate and substrates sequentially stacked on the silicon semiconductor substrate. For example, the stacked substrates may be epitaxial layers, formed by an epitaxial process. Electrical characteristics of substrates formed through the epitaxial process are different from those of a silicon substrate. Typically, substrates formed through the epitaxial process have lower electrical performance characteristics than a silicon substrate. This means that performance and/or reliability of a 3D memory device (e.g., having one or more epitaxial layers) may be inferior to that of a two-dimensional memory device formed on a single silicon substrate.